# top parameter and interface files — include any common
${PROJECT_PATH}/include/param.svh
${PROJECT_PATH}/include/dtype.svh
${PROJECT_PATH}/include/isa.svh
${PROJECT_PATH}/design/common/common_delay_line.sv
${PROJECT_PATH}/design/common/common_fifo.sv
${PROJECT_PATH}/design/common/common_ram_2r1w.sv

# packages and interfaces first
${PROJECT_PATH}/design/ub/ub_param.svh
${PROJECT_PATH}/design/lpu/lpu_intf.svh
${PROJECT_PATH}/design/lpu/lpu_struct.svh
///////////////////////////////////////////////////////////////////
# 1. test mxu
// # module-specific interfaces
// src/aru_arb_rdgen/aru_arb_rdgen_intf.svh

# low-level RTL
# FPU SystemVerilog wrappers (VHDL files compiled separately via vhdl_files.f)
${PROJECT_PATH}/design/fpu/bf16_fpmult.sv
${PROJECT_PATH}/design/fpu/bf16_add.sv

# UB modules
${PROJECT_PATH}/design/ub/ub_atomic_alu.sv
${PROJECT_PATH}/design/ub/ub_atomic_rdgen.sv
${PROJECT_PATH}/design/ub/ub_ram.sv
${PROJECT_PATH}/design/ub/ub_wr_arbiter.sv
${PROJECT_PATH}/design/ub/ub_rd_arbiter.sv
${PROJECT_PATH}/design/ub/ub.sv

# tb
tb/ub_tb.sv
///////////////////////////////////////////////////////////////////
